* Sensor front-end / ADC divider sample - input range validation
* Portfolio sample asset. 5 V sensor scaled by 33k/(22k+33k) = 0.60, so ADC node peaks near 3.0 V.
* Human validation note: the corrected divider leaves headroom below a 3.3 V ADC rail before tolerance review.

Vsensor SENSOR 0 PULSE(0 5 0 1u 1u 2m 4m)
Rtop SENSOR ADC 22k
Rbot ADC 0 33k

* ADC sample-and-hold approximation: small input capacitance with high leakage resistance.
Cadc ADC 0 12p
Radc ADC 0 10Meg

* Optional clamp representation for reasoning about overvoltage risk.
Dclamp ADC VDD DCLAMP
Vdd VDD 0 DC 3.3

.model DCLAMP D(IS=1n RS=2 CJO=2p BV=6 IBV=1u)

.tran 2u 8m

.control
run
set wr_singlescale
set wr_vecnames
wrdata eda-portfolio/evidence/ngspice/adc-divider-output.csv v(SENSOR) v(ADC) i(Vdd)
quit
.endc

.end