MOSFET Haptic Driver
Checks gate drive, pulldown behavior, motor R-L load response, and flyback clamp path.
Source `.cir`
EDA portfolio / inspectable sample assets
EDA Design & Simulation Sample Portfolio
Reproducible electronics design assets covering schematic reasoning, SPICE-readable netlists, PCB handoff structure, and AI-generated EDA asset validation.
Reviewer path: Start with the ESP32 Wearable Haptic Controller, open the MOSFET driver simulation,
compare the waveform to the validation notes, then review the AI EDA rubric.
5
documented circuit assets
5
SPICE-readable netlists
8+
downloadable review artifacts
1
AI EDA validation rubric
Scope note
These are portfolio sample assets created to demonstrate electronics design reasoning, SPICE-readable source files, PCB handoff structure, and AI evaluation workflows. They are not presented as prior employer/client deliverables or manufactured production boards.
Minimum proof checklist
Verifiable evidence before visual polish.
The application-ready gate is file-based: KiCad and Ngspice versions are captured, the KiCad project exports, ERC is clean, Ngspice runs in batch mode, and the validation notes explain expected versus observed behavior.
Flagship artifact
ESP32 Wearable Haptic Controller
A focused motor-driver boundary: ESP32-style GPIO, gate resistor, pulldown, N-channel MOSFET, R-L vibration motor model, flyback diode, local decoupling, and connector-level PCB review notes.
Circuit simulation samples
Small circuits, inspectable reasoning.
Each sample is scoped so a reviewer can check the source file, expected behavior, and likely AI failure mode quickly.
RC Low-Pass Filter
Checks cutoff-frequency calculation against a 10k / 10 nF first-order filter.
Source `.cir`Op-Amp Gain Stage
Checks non-inverting gain reasoning, output swing, and saturation awareness.
Source `.cir`Buck Converter Behavior
Checks switching-node behavior, diode loss, output settling, and component-sizing assumptions.
Source `.cir`Sensor Front-End / ADC Divider
Checks worst-case input range and whether generated values protect a 3.3 V ADC.
Source `.cir`AI EDA evaluation pack
AI EDA Evaluation Pack
The differentiator: a practical rubric for grading generated circuit assets. Any AI-generated EDA asset shown here must be labeled as AI-generated and must include a human validation note before being presented as corrected or acceptable.
| Failure Type | Broken Asset | Evaluator Must Catch |
|---|---|---|
| Missing flyback diode | MOSFET motor driver without clamp path | Inductive kickback risk |
| Wrong RC cutoff | Filter values do not match claimed frequency | `1 / (2*pi*R*C)` mismatch |
| ADC overvoltage | 5 V sensor into 3.3 V ADC range | Divider ratio and max input violation |
| Floating op-amp input | Amplifier lacks defined bias/reference path | Undefined operating point |
Evidence package
Evidence package for technical review.
Direct links resolve locally, while Tiny Sentinel links point to the public repository and live GDS viewer as source-of-truth evidence.
| Asset | Format | Purpose |
|---|---|---|
| ESP32 KiCad project folder | `.kicad_pro` / `.kicad_sch` | Native schematic handoff and export source |
| Schematic export | `.pdf` | Reviewer-friendly KiCad export |
| KiCad ERC report | `.txt` | 0-error / 0-warning electrical-rule-check output |
| Flagship BOM | `.md` | Representative components and review notes |
| MOSFET driver netlist | `.cir` | Transient motor-driver simulation setup |
| RC low-pass netlist | `.cir` | AC cutoff-frequency simulation |
| Op-amp gain-stage netlist | `.cir` | Closed-loop gain simulation |
| Buck converter netlist | `.cir` | Behavior-level switching transient simulation |
| ADC divider netlist | `.cir` | Input-range validation simulation |
| MOSFET output data | `.csv` | Generated Ngspice batch output |
| MOSFET waveform | `.png` | Plot rendered from generated output data |
| RC response plot | `.png` | AC sweep visualization |
| Op-amp waveform | `.png` | Transient input/output validation |
| Buck waveform | `.png` | Switch-node and output-voltage visualization |
| ADC divider waveform | `.png` | Input and scaled ADC node visualization |
| Validation README | `.md` | Expected vs observed behavior |
| AI EDA rubric | `.md` | Scoring generated EDA assets |
| Board handoff checklist | `.md` | PCB review workflow |
| Ngspice rerun script | `.sh` | Batch simulation and plot regeneration |
Adjacent silicon evidence
Tiny Sentinel
Tiny Sentinel is a one-tile TinyTapeout hardware sensor-integrity watchdog that monitors an 8-bit sensor stream and flags spike, stuck-at, and slow-drift anomalies using synthesizable Verilog, deterministic logic, cocotb verification, waveform inspection, and a generated GDS viewer.
This is adjacent digital hardware/ASIC workflow evidence, not PCB layout or SPICE simulation evidence.
This portfolio includes locally linked KiCad and Ngspice evidence artifacts. LibrePCB and Qucs-S native artifacts are planned extensions and are not claimed as completed unless separately verified.